A high-performance flexible architecture for cryptography

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1717, Issue , 1999, Pages 231-245

  Taylor, R Reed ^a   Goldstein, Seth Copen ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Carnegie Mellon University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; EMBEDDED SYSTEMS; GENERAL PURPOSE COMPUTERS; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

AES ALGORITHMS; CRYPTOGRAPHIC ALGORITHMS; CUSTOM HARDWARES; FLEXIBLE ARCHITECTURES; GENERAL PURPOSE PROCESSORS; HARDWARE IMPLEMENTATIONS; RECONFIGURABLE COMPUTING; RECONFIGURABLE FABRICS;

CRYPTOGRAPHY;

EID: 84949527217     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48059-5_20     Document Type: Conference Paper

References (34)

1. C. Adams. The CAST-256 encryption algorithm. www.entrust.com/resources/pdf/cast-256.pdf.
2. R. Anderson, E. Biham, and L. Knudsen. SERPENT. www.cl.cam.ac.uk/~rja14/serpent.html.
3. E. Biham, A. Biryukov, N. Ferguson, L. Knudsen, B. Schneier, and A. Shamir. Cryptanalysis of MAGENTA. www.ii.uib.no/~larsr/papers/magenta.pdf.
4. T. Blum and C. Paar. Montgomery modular exponentiation on reconfigurable hardware. In Proceedings of the 14th IEEE Symposium on Computer Arithmetic (ARITH-14), Adelaide, Australia, April 1999.
5. L. Brown and J. Pieprzyk. Introducing the new LOKI97 Block Cipher. www.adfa.oz.au/~lpb/research/loki97/.
6. M. Budiu and S.C. Goldstein. Fast compilation for pipelined reconfigurable fabrics. In Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, Feb. 1999.
7. Burwick, Coppersmith, D'Avignon, Gennaro, Halevi, Jutla, Matyas Jr., O'Connor, Peyravian, and Safford, Zunic. MARS - a candidate cipher for AES. www.research.ibm.com/security/mars.html.
8. D. Cherepacha and D. Lewis. A datapath oriented architecture for FPGAs. In Second Int'l ACM/SIGDA Workshop on Field Programmable Gate Arrays, 1994.
9. Cylink Corporation. SAFER+. www.cylink.com/SAFER.
10. J. Daemen and V. Rijmen. AES Proposal: Rijndael. www.esat.kuleuven.ac.be/~rijmen/rijndael/.
11. D. Georgoudis, D. Leroux, and B.S. Chaves. The "FROG" encryption algorithm. www.tecapro.com/aesfrog.htm.
12. S.C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, and R. Laufer. Piperench: A coprocessor for streaming multimedia acceleration. In Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 28-39, May 1999.
13. S. Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao. The Chimaera reconfigurable functional unit. In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'97), pages 87-96, April 1997.
14. J.R. Hauser and J. Wawrzynek. Garp: A MIPS processor with a reconfigurable coprocessor. In IEEE Symposium on FPGAs for Custom Computing Machines, pages 24-33, April 1997.
15. Kevin Jaget. Cvhasm: An assembler for pipelined reconfigurable architectures. Master's thesis, Carnegie Mellon University, 1998.
16. J.-P. Kaps and C. Paar. Fast DES implementation for FPGAs and its application to a universal key-search machine. In Selected Areas in Cryptography '98, volume 1556 of Lecture Notes in Computer Science, Kingston, Ontario, Canada, August 1998. Springer-Verlag.
17. L. Knudsen. DEAL: A 128-bit block cipher. Technical Report 151, Department of Informatics,University of Bergen, Norway, Feb 1998.
18. X. Lai and J.L. Massey. A proposal for a new block encryption standard. In Advances in Cryptology Eurocrypt '90, pages 389-404, 1991.
19. J. Leonard and W. H. Mangione-Smith. A case study of partially evaluated hardware circuits: Key-specific DES. In Field-programmable Logic and Applications: 7th International Workshop (FPL'97), London, UK, September 1997.
20. C. H. Lim. "CRYPTON". crypt.future.co.kr/~chlim/crypton.html.
21. H. Lipmaa. IDEA: A cipher for multimedia architectures? In Selected Areas in Cryptography '98, volume 1556 of Lecture Notes in Computer Science, pages 248263, Kingston, Ontario, Canada, August 1998. Springer-Verlag.
22. Ascom Systec Ltd. IDEACrypt Kernel. www.ascom.ch/infosec/idea/kernel.html.
23. B. Preneel, V. Rijmen, and A. Bosselaers. Recent developments in the design of conventional cryptographic algorithms. In Computer Security and Industrial Cryptography, volume 1528 of Lecture Notes in Computer Science, pages 106-131. Springer-Verlag, 1998.
24. R. Razdan and M.D. Smith. A high-performance microarchitecture with hardware-programmable functional units. In MICRO-27, pages 172-180, November 1994.
25. R. Rivest, M.J.B. Robshaw, R. Sidney, and Y.L. Yin. The RC6 Block Cipher. theory.lcs.mit.edu/~rivest/rc6.ps.
26. Herman Schmit. Incremental reconfiguration for pipelined applications. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 47-55, Napa, CA, April 1997.
27. Schneier, Kelsey, Whiting, Wagner, Hall, and Ferguson. Twofish: A 128-bit block cipher. www.counterpane.com/twofish.html.
28. Bruce Schneier. Applied cryptography: Protocols, algorithms, and source code in C, chapter 13, pages 319-325. John Wiley and Sons, Inc., 1996.
29. R. Schroppel. The Hasty Pudding Cipher. www.cs.arizona.edu/~rcs/hpc.
30. M. Shand and J. Vuillemin. Fast implementations of RSA cryptography. In 11th IEEE Symposium on COMPUTER ARITHMETIC, 1993.
31. Nippon Telegraph and Telephone Corporation. The 128-bit block cipher E2. info.isl.ntt.co.jp/e2/.
32. K. W. Tse, T. I. Yuk, and S. S. Chan. Implementation of the data encryption standard algorithm with FPGAs. In W. Moore and W. Luk, editors, More FPGAs: Proceedings of the 1993 International workshop on field-programmable logic and applications, pages 412-419, Oxford, England, September 1993.
33. S. Vaudenay. DFC. www.dmi.ens.fr/~vaudenay/dfc.html.
34. R. Wittig and P. Chow. OneChip: An FPGA processor with reconfigurable logic. In IEEE Symposium on FPGAs for Custom Computing Machines, 1996.