Design of transport triggered architecture processor for discrete cosine transform

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2002, Pages 87-91

  Heikkinen, Jari ^a   Sertamo, Jaakko ^a   Rautiainen, Tino ^a   Takala, Jarmo ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; DESIGN; DISCRETE COSINE TRANSFORMS; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUIT DESIGN; PROGRAM PROCESSORS; SIGNAL PROCESSING;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSOR; CUSTOMIZABLE; DESIGN METHODOLOGY; HARDWARE RESOURCES; PROGRAM EXECUTION; PROGRAMMABLE ARCHITECTURES; SEMI-AUTOMATICS; TRANSPORT TRIGGERED ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 84949450072     PISSN: 10630988     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASIC.2002.1158036     Document Type: Article

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