Optimal self-testing embedded parity checkers

IEEE Transactions on Computers

Volumn 47, Issue 3, 1998, Pages 313-321

  Nikolos, Dimitris ^a,b  

^a IEEE   (Greece)

^b UNIVERSITY OF PATRAS   (Greece)

Author keywords

Embedded self testing circuits; Parity checker; Parity tree; Self testing; Two rail checker

Indexed keywords

COMPUTER ARCHITECTURE; COST EFFECTIVENESS; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC CIRCUITS; LOGIC GATES; OPTIMAL CONTROL SYSTEMS; VECTORS;

SELF CHECKING CIRCUITS (SCC); SELF TESTING EMBEDDED (STE) PARITY CHECKERS;

COMPUTER TESTING;

EID: 0032025356     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.660167     Document Type: Article

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