Experimental and theoretical study of layered tunnel barriers for nonvolatile memories

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 509-512

  Buckley, J ^a   De Salvo, B ^a   Molas, G ^a   Gely M ^a   Deleonibus, S ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; GATES (TRANSISTOR); MOS DEVICES; PERMITTIVITY; SILICA; TUNNEL DIODES;

ELECTRICAL THICKNESS; FIELD SENSITIVITY; GATE STACKS; TUNNEL BARRIERS;

NONVOLATILE STORAGE;

EID: 33751419226     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546696     Document Type: Conference Paper

References (10)

1. International Technology Roadmap for Semiconductors, 2003 Edition.
2. K.K. Likharev, Applied Physics Letters, Vol. 73, No. 15, p. 2137 (1998)
3. P. Blomme et al., Proc. of Dev. Research Confer., p.153 (2002)
4. M. Specht et al., ESSDERC 2002, pp. 599-602 (2002)
5. M. Specht et al., ESSDERC 2002, pp. 599-602 (2002)
6. J. Buckley et al., Silicon Nanoelectronics Workshop 2004
7. B. De Salvo et al., IEEE Transactions on Electron Devices, Vol.48, No. 8, p.1789 (2001)
8. P.K. Roy et al., Applied Physics Letters, Vol. 72, No. 22, p.2835
9. G. Lucovsky, Microelec. Reliability, Vol. 43, Iss.9-11, p.1417 (2003)
10. J. Robertson, Journal of non-crystalline solids, Vol. 303, p. 94 (2002)