Modeling MOSFET and circuit degradation through SPICE

Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference

Volumn 2005, Issue , 2005, Pages 403-406

  Cester, Andrea ^a   Gerardin, Simone ^a   Paccagnella, Alessandro ^a   Ghidini, Gabriella ^b  

^a UNIVERSITY OF PADOVA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DEGRADATION; INTEGRATED CIRCUIT MANUFACTURE; MATHEMATICAL MODELS; PARAMETER ESTIMATION;

CURRENT MIRROR; ELECTRICAL STRESS; LEVEL 3 MODEL; MOSFET DEGRADATION;

MOSFET DEVICES;

EID: 33751410328     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2005.1546670     Document Type: Conference Paper

References (9)

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