Interface and gate line edge roughness effects on intra die variance in MOS device characteristics

Device Research Conference - Conference Digest, DRC

Volumn 2005, Issue , 2005, Pages 83-84

  Gunther, Norman ^a   Hamadeh, Emad ^a,b   Niemann, Darrell ^a   Rahman, Mahmud ^a  

^a SCU   (United States)

^b Applied Micro Circuits Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE ROUGHNESS WAVENUMBER; LINE EDGE ROUGHNESS (LER); ONSET OF STRONG INVERSION (OSI); STANDARD DEVIATION;

COMPUTER AIDED DESIGN; FAST FOURIER TRANSFORMS; MOS DEVICES; STATISTICAL METHODS; SURFACE ROUGHNESS; THRESHOLD VOLTAGE;

GATES (TRANSISTOR);

EID: 33751348789     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2005.1553066     Document Type: Conference Paper

References (10)

1. M. Borici, J. R. Watling, R. C. W. Wilkins, L. Yang, J. R. Barker, and A. Asenov, Semiconductor Science and Technology, 19S, pp.155-157, 2004.
2. J. Fonseca, S. Kaya, DRC, pp. 65-66, 2004.
3. P. Oldiges, Lin Qimghuamg, K. Petrillo, M. Sanchez, M. Ieong, and M. Hargrove, SISPAD, pp. 131-134, 2000.
4. A. Asenov, S. Kaya, SISPAD, pp. 135-138, 2000.
5. C. Rafferty, B. Biegel, Z. Yu, M. Ancona, J. Bude, and R. Dutton, SISPAD, pp. 137-140, 1998.
6. N. Gunther, A. Mutlu, and M. Rahman, J. Appl. Phys., pp. 2063-2072, 2004.
7. A. Asenov, S. Kaya and A. R. Brown, IEEE Trans. Electron Dev., Vol. 50, pp.1254-1260, 2003.
8. A. Asenov, A. R. Brown J. H. Davies, S. Kaya, and G. Slavcheva, IEEE Trans. Electron Dev. Vol. 50, pp. 1837-1852, 2003.
9. th ISQED, San Jose, CA, March 21-23, pp. 510-515, 2005.
10. S.-D. Kim, H. Wada, J. C. S. Woo, IEEE Transactions On Semiconductor Manufacturing, Vol. 17, No. 2, 2004.