Delay testing with double observations

Proceedings of the Asian Test Symposium

Volumn , Issue , 1998, Pages 96-100

  Li, Huawei ^a   Li, Zhongcheng ^a   Min, Yinghua ^a  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY TESTING; SAMPLE PATHS;

COMBINATORIAL CIRCUITS; ELECTRIC FAULT LOCATION; SEMICONDUCTOR DEVICE MODELS;

INTEGRATED CIRCUIT TESTING;

EID: 0032298891     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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3. J.J. Shedletsky, "Delay Testing LSI Logic", RC 6828, IBM T. J. Watson Res. Cent, York town Heights, NY, Oct. 4, 1977.
4. Y. Min, Z. Li, and Z. Zhao, "Boolean Process", Science in China, Series E, Vol. 40, No.3, June 1997, pp. 250-257.
5. W.B. Jone and Y.P. Ho, "Delay Fault Coverage Enhancement Using Variable Observation Times", Journal of Electronic Testing: Theory and Applications 5, 131-146(1997).
6. G.L. Smith, "Model for Delay Faults Based Upon Paths", Intl. Test Conf. Nov. 1985, pp. 342-349.
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8. H.C. Wittmann and M. Henftling, "Efficient Path Identification for Delay Testing-Time and Space Optimization", -proceeding of European Design & Test Conference, pp.513-517, February , 1994.
9. Wangning Long, Z. Li, S. Yang and Y. Min, "Memory Efficient ATP G for Path Delay Faults", Proc. ATS'97, Japan, 1997.
10. E.S. Park, M.R. Mercer, and T.W. Williams, "The Total Delay Fault Model and Statistical Delay Fault Coverage", IEEE Trans, on Computers, Vol.41, pp. 688- 698, June, 1992.