Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2000, Pages

  Zhao, Min ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; INTEGER PROGRAMMING; LOGIC DESIGN;

DOMINO LOGIC; DUAL-MONOTONIC GATES;

LOGIC GATES;

EID: 0033683885     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856323     Document Type: Conference Paper

References (7)