Technology mapping for domino logic

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 248-251

  Zhao, Min ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK SYNTHESIS; LOGIC CIRCUITS; LOGIC GATES; PARAMETER ESTIMATION;

DOMINO LOGIC MAPPING;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032314734     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/288548.288621     Document Type: Conference Paper

References (10)