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Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 820-825

Post-layout logic optimization of Domino circuits

(2) Cao, Aiqun a Koh, Cheng Kok a

a PURDUE UNIVERSITY (United States)

Author keywords

Domino logic; Layout; Optimization; Synthesis

Indexed keywords

COSTS; DESIGN AIDS; ELECTRIC INVERTERS; ELECTRIC POWER UTILIZATION; ITERATIVE METHODS; LOGIC CIRCUITS; OPTIMIZATION;

AUTOMATIC SYNTHESIS; BUBBLE PUSHING; DOMINO LOGIC; TRAPPED INVERTERS;

INTEGRATED CIRCUIT LAYOUT;

EID: 4444272768 PISSN: 0738100X EISSN: None Source Type: Conference Proceeding
DOI: 10.1145/996566.996786 Document Type: Conference Paper

Times cited : (3)

References (8)

1
- 0347409200
- Fractional cut: Improved recursive bisection placement
- Nov.
- A. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, and P. H. Madden. Fractional cut: improved recursive bisection placement. In Proc. Int. Conf. on Computer Aided Design, Nov. 2003.
- (2003) Proc. Int. Conf. on Computer Aided Design
- Agnihotri, A.¹ Yildiz, M.C.² Khatkhate, A.³ Mathur, A.⁴ Ono, S.⁵ Madden, P.H.⁶

2
- 0036474528
- Domino logic synthesis based on implication graph
- Feb.
- K. W. Kim, T. Kim, C. L. Liu, and S. M. Kang. Domino logic synthesis based on implication graph. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 21(2):232-240, Feb. 2002.
- (2002) IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems , vol.21 , Issue.2 , pp. 232-240
- Kim, K.W.¹ Kim, T.² Liu, C.L.³ Kang, S.M.⁴

3
- 0032690069
- Automated phase assignment for the synthesis of low power Domino circuits
- June
- P. Patra and U. Narayanan. Automated phase assignment for the synthesis of low power Domino circuits. In Proc. Design Automation Conf, pages 379-384, June 1999.
- (1999) Proc. Design Automation Conf , pp. 379-384
- Patra, P.¹ Narayanan, U.²

4
- 0003233057
- Domino logic synthesis and technology mapping
- May
- M. R. Prasad, D. Kirkpatrick, R. K. Brayton, and A. Sangiovanni-Vincentelli. Domino logic synthesis and technology mapping. In Proc. Int. Workshop on Logic Synthesis, May 1997.
- (1997) Proc. Int. Workshop on Logic Synthesis
- Prasad, M.R.¹ Kirkpatrick, D.² Brayton, R.K.³ Sangiovanni-Vincentelli, A.⁴

5
- 0032301987
- Design issues in mixed Static-Domino circuit implementations
- Oct.
- R. Puri. Design issues in mixed Static-Domino circuit implementations. In Proc. IEEE Int. Conf. on Computer Design, pages 270-275, Oct. 1998.
- (1998) Proc. IEEE Int. Conf. on Computer Design , pp. 270-275
- Puri, R.¹

6
- 0030385995
- Logic optimization by output phase assignment in dynamic logic synthesis
- Nov.
- R. Puri, A. Bjorksten, and T. E. Rosser. Logic optimization by output phase assignment in dynamic logic synthesis. In Proc. Int. Conf. on Computer Aided Design, pages 2-8, Nov. 1996.
- (1996) Proc. Int. Conf. on Computer Aided Design , pp. 2-8
- Puri, R.¹ Bjorksten, A.² Rosser, T.E.³

7
- 0015681902
- Complete test sets for logic functions
- Nov.
- S. M. Reddy. Complete test sets for logic functions. IEEE Trans. on Computers, C-22(11):1016-1020, Nov. 1973.
- (1973) IEEE Trans. on Computers , vol.C-22 , Issue.11 , pp. 1016-1020
- Reddy, S.M.¹

8
- 0033683885
- Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic
- May
- M. Zhao and S. S. Sapatnekar. Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic. In Proc. IEEE Int. Symp. on Circuits and Systems, pages 309-312, May 2000.
- (2000) Proc. IEEE Int. Symp. on Circuits and Systems , pp. 309-312
- Zhao, M.¹ Sapatnekar, S.S.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.