Logic optimization by output phase assignment in dynamic logic synthesis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 2-8

  Puri, Ruchir ^a   Bjorksten, Andrew ^a   Rosser, Thomas E ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC INVERTERS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; OPTIMIZATION;

DOMINO LOGIC; DYNAMIC LOGIC SYNTHESIS; NONINVERTING LOGIC; TECHNOLOGY MAPPING;

COMPUTER AIDED LOGIC DESIGN;

EID: 0030385995     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)