Design issues in mixed static-domino circuit implementations

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 270-275

  Puri, Ruchir ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CONSTRAINT THEORY; LOGIC DESIGN; LOGIC GATES; MICROPROCESSOR CHIPS; SIMULATION; TIMING CIRCUITS;

MIXED STATIC DOMINO CIRCUIT; TIMING CONSTRAINT;

TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

EID: 0032301987     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)