Low-power cache organization through selective tag translation for embedded processors with virtual memory support

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn 2006, Issue , 2006, Pages 398-403

  Zhou, Xiangrong ^a   Petrov, Peter ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Algorithms; Design; Experimentation; Performance

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRONIC COMMUNITIES; EMBEDDED SYSTEMS; ENERGY CONSERVATION; PROBLEM SOLVING; PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER);

DATA CACHES; HARDWARE ARCHITECTURE; SHARED DATA; VIRTUAL MEMORY;

BUFFER STORAGE;

EID: 33750918294     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1127908.1127999     Document Type: Conference Paper

References (10)

1. B. Jacob and T. Mudge, "Virtual memory: issues of implementation", IEEE Computer, vol. 31, n. 6, pp. 33-43, June 1998.
2. M. Ekman, F. Dahlgren and P. Stenstrom, "TLB and snoop energy-reduction using virtual caches in low-power chip-microprocessors", in ISLPED, pp. 243-246, August 2002.
3. M. Cekleov and M. Dubois, "Virtual-address caches. Part 1: problems and solutions in uniprocessors", IEEE Micro, vol. 17, n. 5, pp. 64-71, September 1997.
4. X. Qiu and M. Dubois, "Towards virtually-addressed memory hierarchies", in HPCA, pp. 51-62, January 2001.
5. J. Kim, S. Min, S. Jeon, B. Ahn, D. Jeong and C. Kim, "U-cache: a cost-effective solution to synonym problem", in HPCA, pp. 243-252, January 1995.
6. P. Petrov, D. Tracy and A. Orailoglu, "Energy-Efficient Physically Tagged Caches for Embedded Processors with Virtual Memory", in Design Automation Conference, pp. 17-22, June 2005.
7. J. H. Lee, J. S. Lee, S. Jeong and S. Kim, "A banked-promotion TLB for high performance and low power", in ICCD, pp. 118-123, September 2001.
8. M. Kandemir, I. Kadayif and G. Chen, "Compiler-Directed Code Restructuring for Reducing Data TLB Energy", in International Conference on Hardware/Software Codedesign and System Synthesis, CODES+ISSS, pp. 98-103, September 2004.
9. G. Reinman and N. Jouppi, "An Integrated Cache Timing and Power Model", Technical report, Western Research Lab, 1999.
10. C. Lee, M. Potkonjak and W. H. Mangione-Smith, "Media-Bench: A Tool for evaluating and synthesizing multimedia and communications systems", in Proceedings of the 30th International Symposium on Microarchitecture, pp. 330-335, December 1997.