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Volumn , Issue , 2004, Pages 98-103

Compiler-directed code restructuring for reducing data TLB energy

Author keywords

Code restructuring

Indexed keywords

BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SOFTWARE; ENERGY UTILIZATION; MULTIPROCESSING SYSTEMS;

EID: 16244423354     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016747     Document Type: Conference Paper
Times cited : (21)

References (17)
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    • Department of Computer Science, UW
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    • (1996) Technical Report , vol.CS-TR-1996-1308
    • Burger, D.1    Austin, T.M.2    Bennett, S.3
  • 3
    • 0026918397 scopus 로고
    • Eliminating, address translation bottleneck for physical address cache
    • T.-C. Chiueh and R. H. Katz. Eliminating, address translation bottleneck for physical address cache. In Proceedings of ASPLOS, 1992.
    • (1992) Proceedings of ASPLOS
    • Chiueh, T.-C.1    Katz, R.H.2
  • 7
    • 84948983281 scopus 로고    scopus 로고
    • Intel StrongArm Processor. http://www.intel.com/design/pca/ applicationsprocessors/1110_brf.htm.
    • Intel StrongArm Processor
  • 10
    • 16244370958 scopus 로고
    • Segmented virtual to real translation assist
    • July
    • J. Knight and P. Rosenfeld. Segmented virtual to real translation assist. IBM Technical Disclosure Bulletin, 27(2):1077-1078, July 1984.
    • (1984) IBM Technical Disclosure Bulletin , vol.27 , Issue.2 , pp. 1077-1078
    • Knight, J.1    Rosenfeld, P.2
  • 13
    • 0010013829 scopus 로고    scopus 로고
    • Low-power TLB design for high-performance microprocessor
    • Department of Electrical and Computer Engineering and Department of Computer Science, University of Colorado, Boulder, CO
    • S. Manne, A. Klauser, D. Grunwald, and F. Somenzi. Low-power TLB design for high-performance microprocessor. Technical Report, Department of Electrical and Computer Engineering and Department of Computer Science, University of Colorado, Boulder, CO, 1997.
    • (1997) Technical Report
    • Manne, S.1    Klauser, A.2    Grunwald, D.3    Somenzi, F.4
  • 15
    • 2342522490 scopus 로고    scopus 로고
    • CACTI 2.0: An integrated cache timing and power model
    • Compaq WRL
    • G. Reinman and N. P. Jouppi. CACTI 2.0: an integrated cache timing and power model. Research Report 2000/7, Compaq WRL, 2000.
    • (2000) Research Report , vol.2000 , Issue.7
    • Reinman, G.1    Jouppi, N.P.2
  • 16
    • 84949603540 scopus 로고    scopus 로고
    • SH-3 RISC processor family. http://www.hitachieu.com/hel/ecg/products/ micro/32bit/sh_3.html.
    • SH-3 RISC Processor Family


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.