A banked-promotion TLB for high performance and low power

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 118-123

  Lee, Jung Hoon ^a   Lee, Jang Soo ^a   Jeong, Seh Woong ^b   Kim, Shin Dug ^a  

^a Yonsei University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; ENERGY DISSIPATION; ENERGY UTILIZATION; PROGRAM PROCESSORS;

TRANSLATION LOOKASIDE BUFFER (TLB) SYSTEM;

BUFFER STORAGE;

EID: 0035183318     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2001.955013     Document Type: Article

References (11)

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4. Surpassing the TLB performance of superpages with less operating system support
5. The filter cache: An energy efficient memory structure
6. Reducing TLB power requirements
7. Trading speed for low power by choice of supply and threshold voltages
8. Improving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers
9. An integrated cache timing and power model
10. Energy-efficiency of VLSI cache: A comparative study
11. Analytical energy dissipation models for low power caches