메뉴 건너뛰기




Volumn 27, Issue 9, 2006, Pages 1566-1571

General method in the synthesis of ternary double pass-transistor circuits

Author keywords

Double pass transistor logic; Logic synthesis; Multiple valued logic; Switching circuit theory

Indexed keywords

CIRCUIT THEORY; SWITCHING CIRCUITS;

EID: 33750593956     PISSN: 02534177     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (8)

References (14)
  • 1
    • 0021404263 scopus 로고
    • Depletion/enhancement CMOS for a low power family of three-valued logic circuits
    • Heung A, Mouftah H T. Depletion/enhancement CMOS for a low power family of three-valued logic circuits. IEEE J Solid-State Circuits, 1985, 20(2): 609.
    • (1985) IEEE J Solid-State Circuits , vol.20 , Issue.2 , pp. 609
    • Heung, A.1    Mouftah, H.T.2
  • 2
    • 84888069093 scopus 로고    scopus 로고
    • The circuit design of multiple-valued logic voltage-mode adders
    • Thoidis I, Soudris D, Fernandez J, et al. The circuit design of multiple-valued logic voltage-mode adders. Proc of ISCAS, 2001, IV-162.
    • (2001) Proc of ISCAS
    • Thoidis, I.1    Soudris, D.2    Fernandez, J.3
  • 3
    • 0037819428 scopus 로고    scopus 로고
    • A technique for logic design of voltage-mode pass transistor based multi-valued multipleoutput logic circuits
    • Babu H, Islam M, Ali A, et al. A technique for logic design of voltage-mode pass transistor based multi-valued multipleoutput logic circuits. Proc of ISMVL, 2003: 111.
    • (2003) Proc of ISMVL , pp. 111
    • Babu, H.1    Islam, M.2    Ali, A.3
  • 4
    • 0025387136 scopus 로고
    • CMOS ternary logic circuits
    • Wu X, Prosser F. CMOS ternary logic circuits. IEE Proceedings, 1990, 137-G(1): 21.
    • (1990) IEE Proceedings , vol.137 G , Issue.1 , pp. 21
    • Wu, X.1    Prosser, F.2
  • 5
    • 33750596563 scopus 로고    scopus 로고
    • A low-power and highspeed quaternary interconnection link using efficient converters
    • Philippe J M, Pillement S, Sentieys O. A low-power and highspeed quaternary interconnection link using efficient converters. Proc of ISCAS, 2005: 4689.
    • (2005) Proc of ISCAS , pp. 4689
    • Philippe, J.M.1    Pillement, S.2    Sentieys, O.3
  • 6
    • 0021609266 scopus 로고
    • Multiple-valued logic-its status and its future
    • Hurst S L. Multiple-valued logic-its status and its future. IEEE Trans Computers, 1984, C-33(12): 1160.
    • (1984) IEEE Trans Computers , vol.C-33 , Issue.12 , pp. 1160
    • Hurst, S.L.1
  • 7
    • 0027642836 scopus 로고
    • Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic
    • Wu C, Huang H. Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic. IEEE J Solid-State Circuits, 1993, 28(8): 895.
    • (1993) IEEE J Solid-State Circuits , vol.28 , Issue.8 , pp. 895
    • Wu, C.1    Huang, H.2
  • 8
    • 0028429260 scopus 로고
    • CMOS ternary dynamic differential logic
    • Herrfeld A, Hentschke S. CMOS ternary dynamic differential logic. Electron Lett, 1994, 30(10): 762.
    • (1994) Electron Lett , vol.30 , Issue.10 , pp. 762
    • Herrfeld, A.1    Hentschke, S.2
  • 9
    • 0032069854 scopus 로고    scopus 로고
    • CMOS dynamic ternary circuit with full logic swing and zero-static power consumption
    • Toro F, Saletti R. CMOS dynamic ternary circuit with full logic swing and zero-static power consumption. Electron Lett, 1998, 34(11): 1083.
    • (1998) Electron Lett , vol.34 , Issue.11 , pp. 1083
    • Toro, F.1    Saletti, R.2
  • 10
    • 0027694895 scopus 로고
    • A 1.5-ns 32-b CMOS ALU in double pass-transistor logic
    • Suzuki M, Ohkubo N, Shinbo T, et al. A 1.5-ns 32-b CMOS ALU in double pass-transistor logic. IEEE J Solid-State Circuits, 1993, 28(11): 1145.
    • (1993) IEEE J Solid-State Circuits , vol.28 , Issue.11 , pp. 1145
    • Suzuki, M.1    Ohkubo, N.2    Shinbo, T.3
  • 12
    • 0034502029 scopus 로고    scopus 로고
    • A general method in synthesis of pass-transistor circuits
    • Markovic D, Nikolic B, Oklobdzija V G. A general method in synthesis of pass-transistor circuits. Microelectronics Journal, 2000, 31(11/12): 991.
    • (2000) Microelectronics Journal , vol.31 , Issue.11-12 , pp. 991
    • Markovic, D.1    Nikolic, B.2    Oklobdzija, V.G.3
  • 13
    • 23044456956 scopus 로고    scopus 로고
    • Low power CMOS dynamic ternary circuit using double pass-transistor logic
    • in Chinese
    • Hang Guoqiang. Low power CMOS dynamic ternary circuit using double pass-transistor logic. Journal of Zhejiang University (Eng Sci), 2005, 39(6): 882 (in Chinese).
    • (2005) Journal of Zhejiang University (Eng Sci) , vol.39 , Issue.6 , pp. 882
    • Hang, G.1
  • 14
    • 3142751405 scopus 로고    scopus 로고
    • Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit
    • Park S J, Yoon B H, Yoon K S, et al. Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit. Proc of ISMVL, 2004: 198.
    • (2004) Proc of ISMVL , pp. 198
    • Park, S.J.1    Yoon, B.H.2    Yoon, K.S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.