Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2004, Pages 198-203

  Park, Soo Jin ^a   Yoon, Byoung Hee ^a   Yoon, Kwang Sub ^a   Kim, Heung Soo ^a  

^a Inha University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ELECTRIC NETWORK ANALYSIS; ELECTRONICS ENGINEERING; ION IMPLANTATION; LOGIC CIRCUITS; MOS CAPACITORS; MOSFET DEVICES; POWER SUPPLY CIRCUITS; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

DOWN LITERAL CIRCUITS (DLC); MULTI VALUED LOGIC (MLV) CIRCUITS; POWER SUPPLY VOLTAGE; QUATERNARY GATE LOGIC;

LOGIC GATES;

EID: 3142751405     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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