CMOS dynamic ternary circuit with full logic swing and zero-static power consumption

Electronics Letters

Volumn 34, Issue 11, 1998, Pages 1083-1084

  Toto, F ^a   Saletti, R ^a  

^a UNIVERSITY OF PISA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; LOGIC DESIGN; LOGIC GATES; MOSFET DEVICES;

NOISE MARGINS;

LOGIC CIRCUITS;

EID: 0032069854     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980754     Document Type: Article

References (4)

1. YOELI, M., and ROSENFELD, G.: 'Logical design of ternary switching circuits', IEEE Trans. Electronic Comput., 1965, C-14, pp. 19-29
2. CURRENT, K.W.: 'Current-mode CMOS multiple-valued logic circuits', IEEE J. Solid-State Circuits, 1994, SSC-29, (2), pp. 95-107
3. HERRFELD, A., and HENTSCHKE, S.: 'CMOS ternary dynamic differential logic', Electron. Lett., 1994, 30, (10), pp. 762-763
4. WU, C., and HUANG, H.: 'Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic', IEEE J. Solid-State Circuits, 1993, SSC-28, (8), pp. 895-906