Highly-parallel decoding architectures for convolutional turbo codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 10, 2006, Pages 1147-1151

  He, Zhiyong ^a   Fortier, Paul ^a   Roy, Śebastien ^a  

^a UNIVERSITÉ LAVAL   (Canada)

Author keywords

Decoder; Interleaver; Parallel architecture; Turbo code

Indexed keywords

CONVOLUTIONAL CODES; DECODING; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING; STORAGE ALLOCATION (COMPUTER);

DECODING ARCHITECTURES; DECODING SPEEDS; PARALLEL ARCHITECTURE; PARALLEL INTERLEAVES;

TURBO CODES;

EID: 33750582142     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.884172     Document Type: Article

References (14)

1. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: Turbo-codes," in Proc. Int. Conf. Commun. (ICC), 1993, pp. 1064-1070.
2. A. Giulietti, L. van der Perre, and A. Strum, "Parallel turbo coding interleavers: Avoiding collisions in accesses to storage elements," Electron. Lett., vol. 38, no. 5, pp. 232-234, Feb. 2002.
3. L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate," IEEE Trans. Inf. Theory, vol. 20, no. IT-2, pp. 284-287, Mar. 1974.
4. Z. Wang, Z. Chi, and K. K. Parhi, "Area-efficient high-speed decoding schemes for turbo decoders," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 6, pp. 902-912, Dec. 2002.
5. 3GPP2 (3rd Generation Partnership Project 2) Specifications, [Online]. Available: http://3gpp2.com/
6. S. Dolinar and D. Divsalar, "Weight distributions for Turbo codes using random and nonrandom permutations," Telecommun. Data Acquisition (TDA) Progress Rep., vol. 42, no. 122, pp. 56-65, Aug. 15, 1995.
7. Z. Wang, Y. Tang, and Y. Wang, "Low hardware complexity parallel turbo decoder architecture," in Proc, IEEE Int. Symp. Circuits Syst., 2003, pp. 53-56.
8. S. Crozier and P. Guinand, "High-performance low-memory interleaver banks for turbo-codes," in Proc. IEEE 54th Veh. Technol. Conf., 2001, pp. 2394-2398.
9. J. Kwak and K. Lee, "Design of dividable interleaver for parallel decoding in turbo codes," Electron. Lett., vol. 38, no. 22, pp. 1362-1364, Oct. 2002.
10. A. J. Viterbi, "An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes," IEEE J. Sel. Areas Commun., vol. 16, no. 2, pp. 260-264, Feb. 1998.
11. F. Raouafi, A. Dingninou, and C. Berrou, "Saving memory in turbo-decoders using the max-log-MAP algorithm," IEE Colloq. Turbo Codes Dig. Broadcasting - Could It Double Capacity?, pp. 14/1-14/4, 1999, (Ref. No. 1999/165).
12. Y. Wu, B. D. Woerner, and T. K. Blankenship, "Data width requirements in SISO decoding with modulo normalization," IEEE Trans. Commun., vol. 49, no. 11, pp. 1861-1868, Nov. 2001.
13. H. Dawid, G. Gehnen, and H. Meyr, "MAP channel decoding: Algorithm and VLSI architecture," in Proc. Workshop VLSI Signal Process., VI, 1993, pp. 141-149.
14. A. Worm, H. Lamm, and N. Wehn, "A high-speed MAP architecture with optimized memory size and power consumption," in Proc. IEEE Workshop Signal Process. Syst., 2000, pp. 265-274.