Low hardware complexity parallel turbo decoder architecture

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2003, Pages

  Wang, Zhongfeng ^a   Tang, Yiyan ^b   Wang, Yuke ^b  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b The University of Texas at Dallas   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODE DIVISION MULTIPLE ACCESS; PARALLEL PROCESSING SYSTEMS; SATELLITE COMMUNICATION SYSTEMS;

TURBO DECODERS;

DECODING;

EID: 0038789166     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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6. A. J. Viterbi, "An intuitive justification of the MAP decoder for convolutional codes", IEEE Journal on Selected Areas in Communications, vol.16, pp. 260-264, February 1998.
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8. Z. Wang, "Low complexity, high performance Turbo decoder design", Ph.D. dissertation, University of Minnesota, Aug. 2000.
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