Measurement and simulation of stacked die thermal resistances

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn 2006, Issue , 2006, Pages 210-215

  Joiner, Bennett ^a   De Oca, Jose Montes ^b   Neelakantan, Sriram ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b WRIGHT STATE UNIVERSITY   (United States)

Author keywords

Integrated circuit; Multi chip; Package; PBGA; Stacked; Superposition; Thermal; Theta JA

Indexed keywords

DIE CONFIGURATIONS; PLASTIC BALL GRID ARRAY PACKAGE (PBGA); SUPERPOSITION;

COMPUTER SIMULATION; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; HEAT RESISTANCE; INTEGRATED CIRCUITS; MULTICHIP MODULES; PLASTICS; SEMICONDUCTOR JUNCTIONS;

DIES;

EID: 33750139921     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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