Thermal testing of a 3-die stacked chip scale package including evaluation of simplified and complex package geometry finite element models

Proceedings of the 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2004

Volumn , Issue , 2004, Pages 491-498

  Zahn, Bret A ^a  

^a ChipPAC Incorporated   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; COMPUTER SIMULATION; COMPUTER SOFTWARE; DATA REDUCTION; ENERGY DISSIPATION; FINITE ELEMENT METHOD; HEAT LOSSES; HEAT RESISTANCE; HEAT TRANSFER; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MATRIX ALGEBRA; RADIATION EFFECTS; THERMAL CONDUCTIVITY;

JUNCTION TEMPERATURE; THERMAL CONDUCTION ELEMENTS; THERMAL RESISTANCE VALUE; THERMAL TESTING;

CHIP SCALE PACKAGES;

EID: 3843148247     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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