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Volumn 2006, Issue , 2006, Pages 124-129

Design and fabrication of a copper test structure for use as an electrical critical dimension reference

Author keywords

[No Author keywords available]

Indexed keywords

COPPER LINES; ELECTRICAL CRITICAL DIMENSION (ECD); LINEWIDTH; VERTICAL SIDEWALLS;

EID: 33749510718     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.2006.1614288     Document Type: Conference Paper
Times cited : (2)

References (16)
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    • Young, D.1    Christou, A.2
  • 2
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    • Test chip for electrical linewidth of copper-interconnect features and related parameters
    • March
    • M.W. Cresswell et al, "Test chip for electrical linewidth of copper-interconnect features and related parameters", Int. Conference on Microelectronic Test Structures, vol. 14, pp. 183-188, March 2001.
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    • Cresswell, M.W.1
  • 3
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    • Requirements for dual-damascene cu-linewidth resistivity measurements
    • April
    • T. Turner, "Requirements for dual-damascene cu-linewidth resistivity measurements", Solid State Technology, vol. 43, no. 4, pp. 89-94, April 2000.
    • (2000) Solid State Technology , vol.43 , Issue.4 , pp. 89-94
    • Turner, T.1
  • 4
    • 0036565281 scopus 로고    scopus 로고
    • Evaluation of sheet resistance and electrical linewidth measurement techniques for copper damascene interonnect
    • May
    • S. Smith, A.J. Walton, A.W.S. Ross, G.K.H. Bodammer, and J.T.M. Stevenson, "Evaluation of sheet resistance and electrical linewidth measurement techniques for copper damascene interonnect", Solid State Technology, vol. 15, no. 2, pp. 214-222, May 2002.
    • (2002) Solid State Technology , vol.15 , Issue.2 , pp. 214-222
    • Smith, S.1    Walton, A.J.2    Ross, A.W.S.3    Bodammer, G.K.H.4    Stevenson, J.T.M.5
  • 6
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    • Test structures for referencing electrical linewidth measurments to silicon lattice parameters using HRTEM
    • R.A. Alien et al, "Test structures for referencing electrical linewidth measurments to silicon lattice parameters using HRTEM", IEEE Transactions on Semiconductor Manufacturing, vol. 16, no. 2, pp. 239-248, 2003.
    • (2003) IEEE Transactions on Semiconductor Manufacturing , vol.16 , Issue.2 , pp. 239-248
    • Alien, R.A.1
  • 9
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    • R.L. Jackson et al, "Processing and integration of copper interconnects", Solid State Technology, vol. 41, March 1998.
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    • Jackson, R.L.1
  • 10
    • 0004165928 scopus 로고    scopus 로고
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  • 12
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    • Reliability of dielectric barriers in copper damascene applications
    • A.S. Lee et al, "Reliability of dielectric barriers in copper damascene applications", IRW Final Report, pp. 137-138, 2003.
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    • Lee, A.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.