Requirements for dual-damascene Cu-linewidth resistivity measurements

Solid State Technology

Volumn 43, Issue 4, 2000, Pages 89-90,-92,-94,-96

  Turner, Timothy ^a  

^a Keithley Instruments   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; CAPACITANCE MEASUREMENT; CHEMICAL POLISHING; COPPER; ELECTRIC RESISTANCE MEASUREMENT; GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; HEAT RESISTANCE; HEATING; INTEGRATED CIRCUIT MANUFACTURE; MEASUREMENT ERRORS; REFRACTORY METALS;

COPPER LINEWIDTH; DUAL DAMASCENE PROCESSING; SIDEWALL BARRIER; THERMAL COEFFICIENT OF RESISTANCE; VAN DER PAUW SHEET RESISTIVITY;

ELECTRIC CONDUCTIVITY MEASUREMENT;

EID: 0343192464     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (3)

1. X. Lin, D. Pramanik, "Future interconnect technologies and Cu metallization," Solid State Technology, Oct. 1998, pp. 63-79.
2. M. Buehler, "Introduction to Test Structures," Tutorial Short Course, 1996 ICMTS.
3. T. Turner, "Electrical Measurement of IC Device CDs and Alignment," Solid State Technology, June 1998, pp. 115-118.