On improving the performance of a dual sampler based analog input digital phase locked loop (DPLL)

Australian Journal of Electrical and Electronics Engineering

Volumn 3, Issue 1, 2006, Pages 1-6

  Banerjee, T ^a   Sarkar, B C ^a  

^a UNIVERSITY OF BURDWAN   (India)

Author keywords

Digital phase locked loop; Stability criteria and transient response

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; PERFORMANCE; SAMPLING; STABILITY CRITERIA; STRUCTURAL DESIGN;

DIGITAL PHASE LOCKED LOOP; TRANSIENT RESPONSE;

PHASE LOCKED LOOPS;

EID: 33749352328     PISSN: 1448837X     EISSN: None     Source Type: Journal    
DOI: 10.1080/1448837X.2006.11464139     Document Type: Article

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