On the performance of a modified first order tanlock Digital Phase Locked Loop (DPLL)

Journal of Electrical and Electronics Engineering, Australia

Volumn 18, Issue 1, 1998, Pages 21-26

  Hati, R ^a   Hati, A ^a   Sarkar, S ^a,b,c   Sarkar, B C ^a  

^a UNIVERSITY OF BURDWAN   (India)

^b IEEE   (United States)

^c Burdwan Raj College   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL CIRCUITS; SPURIOUS SIGNAL NOISE;

DIGITAL PHASE LOCKED LOOPS (DPLL); PHASE ERROR SENSING CIRCUITS;

PHASE LOCKED LOOPS;

EID: 0032091559     PISSN: 07252986     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)

1. Gardner F M. Phase lock techniques. 2nd ed., New York, Wiley,1979.
2. Lindsey W C, Chie C M. A survey of digital phase locked loops, Proc IEEE, April 1981;69(4):410-431.
3. Rhode V L. Digital PLL frequency synthesizers - theory and design. Englewood Cliffs, NJ, Prentice Hall, 1983.
4. Weinberg A, Liu B. Discrete time analysis of nonuniform sampling first and second order digital phase locked loops. IEEE Trans on Commun, Feb 1974; COM-70 (10):123-137.
5. Sarkar B C, Chattopadhyay S, Sarkar S. Structure and performance of a Tanlock type digital phase locked loop. JEEE (Australia), Sept 1992;12(3):242-247.
6. Hagiwara M, Nakagawa M. Multisampling digital tanlock loop. IEEE Inf. Conf. on Commun. '87 Proceedings, June 1987: 213-217.
7. Cho W D, Un C K. Convergence behaviour of the first order multisampling digital tanlock loop. IEE Proceedings (F), Oct 1988; 35:457-460.
8. Sarkar B C, Chattopadhyay S. Novel quick response digital phase locked loop. Electronics letters (UK), Sept 1988;24(20): 1263-1264.