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Volumn 86, Issue 7, 2006, Pages 1426-1434

A new dynamic gain control algorithm for speed enhancement of digital-phase locked loops (DPLLs)

Author keywords

Loop gain; Transient response, stability criteria; Zero crossing digital phase locked loop (ZC DPLL)

Indexed keywords

ALGORITHMS; DATA ACQUISITION; DIGITAL FILTERS; INVARIANCE; PHASE LOCKED LOOPS; STABILITY CRITERIA;

EID: 33646121279     PISSN: 01651684     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sigpro.2005.07.028     Document Type: Article
Times cited : (10)

References (11)
  • 1
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    • Lindsey, W.C.1    Chie, C.M.2
  • 2
    • 0035311123 scopus 로고    scopus 로고
    • Some advances and refinements in digital phase locked loops (DPLLs)
    • Zoltowski M. Some advances and refinements in digital phase locked loops (DPLLs). Signal Processing 81 (2001) 735-789
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  • 3
    • 17644371632 scopus 로고    scopus 로고
    • Phase error dynamics of a class of DPLLs in presence of co channel interference
    • Banerjee T., and Sarkar B.C. Phase error dynamics of a class of DPLLs in presence of co channel interference. Signal Processing 85 (June 2005) 1139-1147
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    • Banerjee, T.1    Sarkar, B.C.2
  • 4
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    • Phase error dynamics of a class of modified second order digital phase-locked loops in the background of co channel interference
    • Banerjee T., and Sarkar B.C. Phase error dynamics of a class of modified second order digital phase-locked loops in the background of co channel interference. Signal Processing 85 (August 2005) 1611-1622
    • (2005) Signal Processing , vol.85 , pp. 1611-1622
    • Banerjee, T.1    Sarkar, B.C.2
  • 5
    • 0024073448 scopus 로고
    • Novel quick-response digital phase-locked loop
    • Sarkar B.C., and Chattopadhyay S. Novel quick-response digital phase-locked loop. Electron. Lett. 24 (November 1988) 1263-1264
    • (1988) Electron. Lett. , vol.24 , pp. 1263-1264
    • Sarkar, B.C.1    Chattopadhyay, S.2
  • 6
    • 0036287552 scopus 로고    scopus 로고
    • A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers
    • Tang Y., Ismail M., and Bibyk S. A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers. Proceedings-IEEE Internat. Symp. Circuits Systems 4 (2002) IV/787-IV/790
    • (2002) Proceedings-IEEE Internat. Symp. Circuits Systems , vol.4
    • Tang, Y.1    Ismail, M.2    Bibyk, S.3
  • 7
    • 0035493809 scopus 로고    scopus 로고
    • Design and implementation of a low-voltage fast-switching mixed-signal-controlled frequency synthesizer
    • Chiueh T.D., Yang J.-B., and Wu J.-S. Design and implementation of a low-voltage fast-switching mixed-signal-controlled frequency synthesizer. IEEE Trans. Circuits Systems II: Analog Digital Signal Process. 48 10 (2001) 961-971
    • (2001) IEEE Trans. Circuits Systems II: Analog Digital Signal Process. , vol.48 , Issue.10 , pp. 961-971
    • Chiueh, T.D.1    Yang, J.-B.2    Wu, J.-S.3
  • 8
    • 0034795378 scopus 로고    scopus 로고
    • R. Kuppuswamy, K. Callahan, K. Wong, D. Ratchen, G. Taylor, On-die clock jitter detector for high speed microprocessors, IEEE Symposium on VLSI Circuits, Digest of Technical Papers (CIRCUITS SYMP.), 2001, pp. 187-190.
  • 9
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    • Stability analysis of an Nth power digital phase-locked loop-part II: second and third order DPLL's
    • Osborne H.C. Stability analysis of an Nth power digital phase-locked loop-part II: second and third order DPLL's. IEEE Trans. Commun. COM-28 (August 1980) 1355-1364
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    • Osborne, H.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.