A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  Tang, Yiwu ^a   Ismail, Mohammed ^a   Bibyk, Steven ^a  

^a OHIO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE CONTROL SYSTEMS; BANDWIDTH COMPRESSION; COMPUTER SIMULATION; CONTROL SYSTEM SYNTHESIS; ELECTRIC FILTERS; ELECTRIC FREQUENCY CONTROL; FREQUENCY DIVIDING CIRCUITS; FREQUENCY SYNTHESIZERS; MATHEMATICAL MODELS; TRANSFER FUNCTIONS;

FAST SETTLING GEAR SHIFT; LOOP BANDWIDTH ENHANCEMENT; NONLINEAR SAMPLING DELAY MODEL;

PHASE LOCKED LOOPS;

EID: 0036287552     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. An adaptive PLL tuning system architecture combining high spectral purity and fast settling time
2. A low-noise fast-lock phase-locked loop with adaptive bandwidth control
3. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers
4. A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application
5. A low-noise fast-settling PLL with extended loop bandwidth enhancement by new adaptation technique