Enhancing a reconfigurable instruction set processor with partial predication and virtual opcode support

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3985 LNCS, Issue , 2006, Pages 217-229

  Vassiliadis, Nikolaos ^a   Theodoridis, George ^a   Nikolaidis, Spiridon ^a  

^a ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; CODES (SYMBOLS); COMPUTER ARCHITECTURE; IMAGE COMPRESSION; PROGRAM PROCESSORS;

MPEG-2 ENCODERS; RECONFIGURABLE FUNCTIONAL UNIT (RFU); RECONFIGURABLE INSTRUCTION SET PROCESSOR (RISP) ARCHITECTURE; VIRTUAL OPCODE;

COMPUTER SCIENCE;

EID: 33749037133     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11802839_30     Document Type: Conference Paper

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