Software development for high-performance, reconfigurable, embedded multimedia systems

IEEE Design and Test of Computers

Volumn 22, Issue 1, 2005, Pages 28-38

  La Rosa, Alberto ^a   Lavagno, Luciano ^a   Passerone, Claudio ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; REDUCED INSTRUCTION SET COMPUTING;

RECONFIGURABLE ARCHITECTURE; RECONFIGURABLE COMPUTING;

SOFTWARE ENGINEERING;

EID: 14844341529     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2005.20     Document Type: Article

References (5)

1. A. Lodi et al., "A VLIW Processor with Reconfigurable Instruction Set for Embedded Applications," IEEE J. Solid-State Circuits, vol. 38, no. 11, Nov. 2003, pp. 1876-1886.
2. C. Mucci et al., "A C-Based Algorithm Development Flow for a Reconfigurable Processor Architecture," Proc. Int'l Symp. System-on-Chip (SoC 03), IEEE Press, 2003, pp. 69-73.
3. M.C. Valenti and J. Sun, "The UMTS Turbo Code and Efficient Decoder Implementation Suitable for Software-Defined Radios," Int'l J. Wireless Information Networks, vol. 8, no. 4, Oct. 2001, pp. 203-215.
4. T.K. Blankenship and B. Classon, Fixed-Point Performance of Low Complexity Turbo Decoding Algorithms, tech. report, Motorola Labs, 2001.
5. W.J. Ebel, Turbo-Code Implementation on C6x, tech. report, Alexandria Research Inst., Virginia Polytechnic Inst. and State Univ., 1999.