-
1
-
-
24944473744
-
-
ARC Cores, http://www.arccores.com.
-
-
-
-
2
-
-
24944497513
-
-
Gaisler Research, http://www.gaisler.com.
-
-
-
-
3
-
-
24944484915
-
-
Machine-SUIF research compiler. http://www.eecs.harvard.edu/hube/ research/machsuif.html.
-
-
-
-
4
-
-
24944444019
-
-
Pattlib. http://www.lsc.ic.unicamp.br/pattlib/.
-
-
-
-
5
-
-
24944466312
-
-
SUIF, http://suif.stanford.edu/suif/suif2/.
-
-
-
-
8
-
-
0003679064
-
-
MPEG-4 draft standard, International Organization of Standardization, Working Group on Coding of Moving Pictures and Audio, Pisa, Italy, Jan.
-
MPEG-4 video verification model version 18.0. MPEG-4 draft standard, International Organization of Standardization, Working Group on Coding of Moving Pictures and Audio, Pisa, Italy, Jan. 2001.
-
(2001)
MPEG-4 Video Verification Model Version 18.0
-
-
-
10
-
-
0022754418
-
Multiplication by integer constants
-
July
-
R. Bernstein. Multiplication by integer constants. Softw. -Practice and Experience, 16(7):641-652, July 1986.
-
(1986)
Softw. -practice and Experience
, vol.16
, Issue.7
, pp. 641-652
-
-
Bernstein, R.1
-
12
-
-
4444275354
-
Introduction of local memory elements in instruction set extensions
-
June 7-11
-
P. Biswas, V. Choudhary, K. Atasu, L. Pozzi, P. Ienne, and N. Dutt. Introduction of local memory elements in instruction set extensions. In Proc. 41th Design Automation Conf., pages 729-734, June 7-11 2004.
-
(2004)
Proc. 41th Design Automation Conf.
, pp. 729-734
-
-
Biswas, P.1
Choudhary, V.2
Atasu, K.3
Pozzi, L.4
Ienne, P.5
Dutt, N.6
-
13
-
-
0042275094
-
Multiplication by integer constants
-
Rice University, July
-
P. Briggs and T. Harvey. Multiplication by integer constants. Technical report, Rice University, July 1994.
-
(1994)
Technical Report
-
-
Briggs, P.1
Harvey, T.2
-
14
-
-
84937424951
-
BitValue inference: Detecting and exploiting narrow bitwidth computations
-
M. Budiu, M. Sakr, K. Walker, and S. C. Goldstein. BitValue inference: Detecting and exploiting narrow bitwidth computations. In Proc. of the European Conf. on Parallel Processing, pages 969-979, 2000.
-
(2000)
Proc. of the European Conf. on Parallel Processing
, pp. 969-979
-
-
Budiu, M.1
Sakr, M.2
Walker, K.3
Goldstein, S.C.4
-
15
-
-
0003465202
-
The SimpleScalar tool set, version 2.0
-
Computer Sciences Department, University of Wisconsin-Madison, June
-
D. C. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical reportCS-TR-1997-1342, Computer Sciences Department, University of Wisconsin-Madison, June 1997.
-
(1997)
Technical Report
, vol.CS-TR-1997-1342
-
-
Burger, D.C.1
Austin, T.M.2
-
17
-
-
3543121738
-
Automatic design of application specific instruction set extensions through dataflow graph exploration
-
Dec.
-
N. Clark, H. Zhong, W. Tang, and S. Mahlke. Automatic design of application specific instruction set extensions through dataflow graph exploration. Int. J. Parallel Programming, 31(6):429-449, Dec. 2003.
-
(2003)
Int. J. Parallel Programming
, vol.31
, Issue.6
, pp. 429-449
-
-
Clark, N.1
Zhong, H.2
Tang, W.3
Mahlke, S.4
-
19
-
-
0033884908
-
Xtensa: A configurable and extensible processor
-
Man-Apr.
-
R. Gonzalez. Xtensa: A configurable and extensible processor. IEEE Micro, 20:60-70, Man-Apr. 2000.
-
(2000)
IEEE Micro
, vol.20
, pp. 60-70
-
-
Gonzalez, R.1
-
25
-
-
85008063768
-
Bitwidth cognizant architecture synthesis of custom hardware accelerators
-
Nov.
-
S. Mahlke, R. Ravindran, M. Schlansker, R. Schreiber, and T. Sherwood. Bitwidth cognizant architecture synthesis of custom hardware accelerators. IEEE Trans, on Comput.Aided Design Integrated Circuits, 20(11): 1355-1371, Nov. 2001.
-
(2001)
IEEE Trans, on Comput.Aided Design Integrated Circuits
, vol.20
, Issue.11
, pp. 1355-1371
-
-
Mahlke, S.1
Ravindran, R.2
Schlansker, M.3
Schreiber, R.4
Sherwood, T.5
-
27
-
-
4444319771
-
Automatic topology-based identification of instruction-set extensions for embedded processors
-
Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory, Dec.
-
L. Pozzi, M. Vuletic, and P. lenne. Automatic topology-based identification of instruction-set extensions for embedded processors. Technical Report CS 01/377, Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory, Dec. 2001.
-
(2001)
Technical Report
, vol.CS 01-377
-
-
Pozzi, L.1
Vuletic, M.2
Lenne, P.3
-
28
-
-
1242286078
-
Custominstruction synthesis for extensible-processor platforms
-
Feb.
-
F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha. Custominstruction synthesis for extensible-processor platforms. IEEE Trans. on Comput.-Aided Design Integrated Circuits, 23(2):216-228, Feb. 2004.
-
(2004)
IEEE Trans. on Comput.-aided Design Integrated Circuits
, vol.23
, Issue.2
, pp. 216-228
-
-
Sun, F.1
Ravi, S.2
Raghunathan, A.3
Jha, N.K.4
-
29
-
-
0027630094
-
Interlock collapsing ALUs
-
July
-
S. Vassiliadis, J. Philips, and B. Blaner. Interlock collapsing ALUs. IEEE Trans. Comp., 42(7):825-839, July 1993.
-
(1993)
IEEE Trans. Comp.
, vol.42
, Issue.7
, pp. 825-839
-
-
Vassiliadis, S.1
Philips, J.2
Blaner, B.3
-
30
-
-
4444384247
-
Characterizing embedded applications for instruction-set extensible processors
-
June 7-11
-
P. Yu and T. Mitra. Characterizing embedded applications for instruction-set extensible processors. In Proc. 41th Design Automation Conf., pages 723-728, June 7-11 2004.
-
(2004)
Proc. 41th Design Automation Conf.
, pp. 723-728
-
-
Yu, P.1
Mitra, T.2
|