A clustering based area I/O planning for flip-chip technology

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 196-201

  Wang, Janet ^a   Muchherla, Kishore Kumar ^a   Kumar, Jai Ganesh ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; DESIGN; ITERATIVE METHODS; MICROPROCESSOR CHIPS; NANOSTRUCTURED MATERIALS; PACKAGING;

CLUSTERING; I/O PLANNING; PACKAGING TECHNOLOGY; SOC DESIGN;

FLIP CHIP DEVICES;

EID: 2942683259     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2004.1283673     Document Type: Conference Paper

References (9)

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