Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 497-502

  Oh, Hyunok ^a   Dutt, Nikil ^a   Ha, Soonhoi ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; GRAPH THEORY; OPTIMIZATION; SCHEDULING;

BUFFER OPTIMAL SCHEDULE; QUASI-STATIC SCHEDULE; SCHEDULE ALGORITHMS; SYNCHRONOUS DATAFLOW GRAPHS;

OPTIMAL SYSTEMS;

EID: 33748587272     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118420     Document Type: Conference Paper

References (13)

1. COSSAP User's Manual. Synopsys Inc. 700 E. Middlefield Rd. Mountain View,CA94043, USA.
2. M. Ade, R. Lauwereins, and J. A. Peperstraete. Data memory minimization for synchronous data flow graphs emulated on dsp-fpga targets. In DAC, June 1997.
3. S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee. Synthesis of embedded software from synchronous dataflow specifications. In Journal of VLSI Signal Processing, volume 21, pages 151-166, June 1999.
4. J. T. Buck, S. Ha, E. A. Lee, and D. G. Messerschimitt. Ptolemy: A framework for simulating and prototyping heterogeneous systems. In Int. Journal of Computer Simulation, special issue on Simulation Software Development, volume 4, pages 155-182, April 1994.
5. M. Ko, P. K. Murthy, and S. S. Bhattacharyya. Compact procedural implementation in DSP software synthesis through recursive graph decomposition. In Proceedings of the International Workshop on Software and Compilers for Embedded Processors, pages 47-61, Amsterdam, The Netherlands, September 2004.
6. R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. V. Ginderdeuren. Grape: A case tool for digital signal parallel processing. In IEEE ASSP Magazine, volume 7, pages 32-43, April 1990.
7. E. A. Lee and D. G. Messerschmitt. Static scheduling of synchronous dataflow programs for digital signal processing. In IEEE Transaction on Computer, volume C-36, pages 24-35, January 1987.
8. P. K. Murthy and S. S. Bhattacharyya. Shared buffer implementations of signal processing systems using lifetime analysis techniques. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 20, pages 177-198, February 2001.
9. P. K. Murthy, S. S. Bhattachayya, and E. A. Lee. Joint minimization of code and data for synchronous dataflow programs. In Journal of Formal Methods in Systems Design, volume 11, pages 41-70, July 1997.
10. H. Oh, N. Dutt, and S. Ha. Single appearance schedlue with dyanmic loop count for sy. In CASES2005, volume 2005, pages 514-529, Sept 2005.
11. H. Oh and S. Ha. Memory-optimized software synthesis from dataflow program graphs with large size data samples. In EURASIP Journal on Applied Signal Processing, volume 2003, pages 514-529, May 2003.
12. S. Ritz, M. Willems, and H. Meyr. Scheduling for optimum data memory compaction in block diagram oriented software synthesis. In Proceedings of the ICASSP 95, May 1995.
13. W. Sung and S. Ha. Memory efficient software synthesis using mixed coding style from dataflow graph. In IEEE Transaction on VLSI Systems, volume 8, pages 522-526, October 2000.