Advanced numerical and experimental techniques for analysis of dynamic responses and solder joint reliability during drop impact

IEEE Transactions on Components and Packaging Technologies

Volumn 29, Issue 3, 2006, Pages 449-456

  Luan, Jing En ^a   Tee, Tong Yan ^a   Pek, Eric ^b   Lim, Chwee Teck ^b   Zhong, Zhaowei ^c   Zhou, Jiang ^d  

^a STMICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d Lamar University   (United States)

Author keywords

Ball grid array (BGA); Bending; Drop test; Finite element modeling (FEM); Solder joint reliability

Indexed keywords

COMPUTER SIMULATION; DYNAMIC RESPONSE; FAILURE (MECHANICAL); FINITE ELEMENT METHOD; IMPACT TESTING; MATHEMATICAL MODELS; PRINTED CIRCUIT BOARDS; RELIABILITY; SOLDERED JOINTS;

BALL GRID ARRAY; BOARD LEVEL DROP TEST;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 33748543601     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAPT.2006.880455     Document Type: Article

References (27)

1. Board Level Drop Test Method of Components for Handheld Electronic Products, JEDEC Std. JESD22-B111, 2003.
2. Mechanical Shock, JEDEC Std. JESD22-B104-B, 2001.
3. Subassembly Mechanical Shock, JEDEC Std. JESD22-B110, 2001.
4. J. E. Luan, T. Y. Tee, E. Pek, C. T. Lim, and Z. W. Zhong, "Modal analysis and dynamic responses of board level drop test," in Proc. 5th EPTC Conf., Singapore, 2003, pp. 233-243.
5. T. Sogo and S. Hara, "Estimation of fall impact strength for BGA solder joints," in Proc. ICEP Conf., Tokyo, Japan, 2001, pp. 369-373.
6. K. Mishiro, "Effect of the drop impact on bga/csp package reliability," Microelectron. Rel. J., vol. 42, no. 1, pp. 77-82, 2002.
7. C. T. Lim and Y. J. Low, "Drop impact testing of portable electronic products," in Proc. 52nd Electron. Comp. Technol. Conf., San Diego, CA, 2002, pp. 1270-1274.
8. C. T. Lim and Y. J. Low, "Drop impact survey of portable electronic products," in Proc. 53rd Electron. Comp. Technol. Conf., New Orleans, LA, 2003, pp. 113-120.
9. T. Y. Tee, J. E. Luan, E. Pek, C. T. Lim, and Z. W. Zhong, "Novel numerical and experimental analysis of dynamic responses under board level drop test," in Proc. EuroSime Conf., Brussels, Belgium, 2004, pp. 133-140.
10. J. Wu, G. Song, C. Yeh, and K. Wyatt, "Drop/Impact simulation and test validation of telecommunication products," in Proc. Intersoc. Conf. Thermal Phenom., 1998, pp. 330-336.
11. J. Wu, "Global and local coupling analysis for small components in drop simulation," in Proc. 6th Int. LS-DYNA Users Conf., 2000, pp. 11:17-11:26.
12. L. Zhu, "Submodeling technique for BGA reliability analysis of csp packaging subjected to an impact loading," in Proc. InterPACK Conf., Kauai, HI, Jul. 2001, [CD ROM].
13. L. Zhu, "Modeling technique for reliability assessment of portable electronic product subjected to drop impact loads," in Proc. 53rd Electron. Comp. Technol. Conf., New Orleans, LA, 2003, pp. 100-104.
14. T. Y. Tee, H. S. Ng, C. T. Lim, E. Pek, and Z. W. Zhong, "Board level drop test and simulation of TFBGA packages for telecommunication applications," in Proc. 53rd Electron. Comp. Technol. Conf., New Orleans, LA, 2003, pp. 121-129.
15. T. Y. Tee, H. S. Ng, C. T. Lim, E. Pek, and Z. W. Zhong, "Board level drop test and simulation of qfn packages for telecommunication applications," in Proc. ICEP Conf., Tokyo, Japan, 2003, pp. 221-226.
16. T. Y. Tee, H. S. Ng, C. T. Lim, E. Pek, and Z. W. Zhong, "Impact life prediction modeling of TFBGA packages under board level drop test," Microelectron. Rel. J., vol. 44, no. 7, pp. 1131-1142, 2004.
17. T. Y. Tee, H. S. Ng, and Z. W. Zhong, "Design for enhanced solder joint reliability of integrated passives device under board level drop test and thermal cycling test," in Proc. 5th EPTC Conf., Singapore, 2003, pp. 210-216.
18. T. Y. Tee, H. S. Ng, J. E. Luan, D. Yap, K. Loh, E. Pek, C. T. Lim, and Z. W. Zhong, "Integrated modeling and testing of fine-pitch csp under board level drop test, bend test, and thermal cycling test," in Proc. ICEP Conf., Tokyo, Japan, 2004, pp. 35-40.
19. J. E. Luan, T. Y. Tee, X. R. Zhang, and E. Hussa, "Solder joint failure modes, mechanisms, and impact life prediction models of IC packages under board level drop impact," in Proc. Int. Conf. Electron. Packag. Technol. (ICEPT), Shenzhen, China, 2005, pp. 382-388.
20. J. E. Luan, T. Y. Tee, H. S. Ng, K. Y. Goh, X. Baraton, R. Bronner, M. Sorrieul, E. Hussa, T. Reinikainen, and A. Kujala, "Drop impact life prediction model for lead-free BGA packages and modules," in Proc. EuroSIME Conf., Berlin, Germany, 2005, pp. 559-565.
21. T. Y. Tee, H. S. Ng, and J. E. Luan, "Comparison of free-fall vs. input-g drop impact models," in Proc. 6th EMAP Conf., Penang, Malaysia, 2004, pp. 48-55.
22. J. E. Luan and T. Y. Tee, "Analytical and numerical analysis of impact pulse parameters on consistency of drop impact results," in Proc. 6th EPTC Conf., Singapore, 2004, pp. 664-670.
23. J. E. Luan and T. Y. Tee, "Novel board level drop test simulation using implicit transient analysis with input-G method," in Proc. 6th EPTC Conf., Singapore, 2004, pp. 671-677.
24. H. S. Ng, T. Y. Tee, and J. E. Luan, "Design for standard impact pulses of drop tester using dynamic simulation," in Proc. 6th EPTC Conf., Singapore, 2004, pp. 793-799.
25. J. E. Luan and T. Y. Tee, "Effect of impact pulse parameters on consistency of board level drop test and dynamic responses," in Proc. 55th Electron. Comp. Technol. Conf., 2005, pp. 665-673.
26. T. Y. Tee, J. E. Luan, and H. S. Ng, "Development and application of innovational drop impact modeling techniques," in Proc. 55th Electron. Comp. Technol. Conf., 2005, pp. 504-512.
27. K. Y. Goh, J. E. Luan, and T. Y. Tee, "Drop impact life prediction model for wafer level chip scale packages," in Proc. 7th EPTC Conf., Singapore, 2005, pp. 58-65.