Novel board level drop test simulation using implicit transient analysis with input-G method

Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004

Volumn , Issue , 2004, Pages 671-677

  Luan, Jing En ^a  

^a STMICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COST EFFECTIVENESS; FINITE ELEMENT METHOD; MATHEMATICAL MODELS;

CONTACT SURFACES; COST-SAVING; DROP IMPACT LOADING; FREE-FALL MODEL;

ELECTRONICS PACKAGING;

EID: 28444453001     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. JEDEC Standard JESD22-B111, Board Level Drop Test Method of Components for Handheld Electronic Products, 2003.
2. Wu, J., Song, G., Yeh, C., and Wyatt, K., "Drop/Impact Simulation and Test Validation of Telecommunication Products," Proc. of InterSociety Conference on Thermal Phenomena, 1998, pp. 330-336.
3. th International LS-DYNA Users Conference Proc., 2000, pp. 11:17-11:26.
4. Zhu, L., "Submodeling Technique for BGA Reliability Analysis of CSP Packaging Subjected to an Impact Loading," InterPACK Conference Proc., 2001.
5. Sogo, T. and Hara, S., "Estimation of Fall Impact Strength for BGA Solder Joints," ICEP Conference Proc., Japan, 2001, pp. 369-373.
6. rd ECTC Conference Proc., 2003, pp. 121-129.
7. th ECTC Conference Proc., 2004, pp. 1088-1094.
8. th ECTC Conference Proc., 2004, pp. 1062-1066.
9. ANSYS Theoretical Manual, Swanson Analysis Systems, Inc., Houston, PA, 2004.
10. th EPTC Conference Proc., Singapore, 2003, pp. 233-243.