-
1
-
-
9144234352
-
Characterization of soft errors caused by single event upsets in CMOS processes
-
April-June
-
Karnik, T., Hazucha, P., "Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes," IEEE Transactions on Dependable and Secure Computing, VOL. 1, NO. 2, April-June 2004.
-
(2004)
IEEE Transactions on Dependable and Secure Computing
, vol.1
, Issue.2
-
-
Karnik, T.1
Hazucha, P.2
-
2
-
-
0036931372
-
Modeling the effect of technology trends on the soft error rate of combinational logic
-
Shivakumar, P., Kistler, M., Keckler, S.W., Burger, D., Alvisi, L., "Modeling the effect of technology trends on the soft error rate of combinational logic," International Conference on Dependable Systems and Networks, 2002.
-
(2002)
International Conference on Dependable Systems and Networks
-
-
Shivakumar, P.1
Kistler, M.2
Keckler, S.W.3
Burger, D.4
Alvisi, L.5
-
4
-
-
4444365711
-
Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process
-
September
-
Hazucha, P., Karnik, T., Walstra, S., Bloechel, B., Tschanz, J., Maiz, J., Soumyanath, K., Dermer, G., Narendra, S., De, V., Borkar, S., "Measurements and Analysis of SER-Tolerant Latch in a 90-nm Dual-VT CMOS Process," IEEE Journal on Solid State, VOL. 39, NO. 9, September 2004.
-
(2004)
IEEE Journal on Solid State
, vol.39
, Issue.9
-
-
Hazucha, P.1
Karnik, T.2
Walstra, S.3
Bloechel, B.4
Tschanz, J.5
Maiz, J.6
Soumyanath, K.7
Dermer, G.8
Narendra, S.9
De, V.10
Borkar, S.11
-
5
-
-
0036927879
-
The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction
-
Baumann, R., "The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction," Electron Devices Meeting, 2002.
-
(2002)
Electron Devices Meeting
-
-
Baumann, R.1
-
6
-
-
0842266592
-
Characterization of multi-bit soft error events in advanced SRAMs
-
Maiz, J., Hareland, S., Zhang, K., Armstrong, P., "Characterization of multi-bit soft error events in advanced SRAMs," IEEE International Electron Devices Meeting, 2003.
-
(2003)
IEEE International Electron Devices Meeting
-
-
Maiz, J.1
Hareland, S.2
Zhang, K.3
Armstrong, P.4
-
8
-
-
0032122796
-
Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits
-
Tosaka, Y., Satoh, S., Itakura, T., Ehara, H., Ueda, T., Woffinden, G.A., Wender, S.A., "Measurement and Analysis of Neutron-Induced Soft Errors in Sub-Half-Micron CMOS Circuits," IEEE Transactions on Electron Devices VOL 45, 1998.
-
(1998)
IEEE Transactions on Electron Devices VOL 45
, vol.45
-
-
Tosaka, Y.1
Satoh, S.2
Itakura, T.3
Ehara, H.4
Ueda, T.5
Woffinden, G.A.6
Wender, S.A.7
-
10
-
-
33748561589
-
-
70nm BPTM models http://www-device.eecs.berkeley.edu/~ptm/mosfet.html.
-
70nm BPTM Models
-
-
-
11
-
-
1642276264
-
Statistical analysis of subthreshold leakage current for VLSI circuits
-
Rao, R., Srivastava, A., Blaauw, D., Sylvester, D., Statistical analysis of subthreshold leakage current for VLSI circuits, IEEE Transactions on VLSI, VOL. 12, Issue 2, 2004.
-
(2004)
IEEE Transactions on VLSI
, vol.12
, Issue.2
-
-
Rao, R.1
Srivastava, A.2
Blaauw, D.3
Sylvester, D.4
|