Timing analysis of an embedded memory: SPSMALL

WSEAS Transactions on Circuits and Systems

Volumn 5, Issue 7, 2006, Pages 973-978

  Chevallier, Remy ^a   Encrenaz Tiphène, Emmanuelle ^b   Fribourg, Laurent ^b   Xu, Weiwen ^b  

^a STMICROELECTRONICS   (France)

^b CNRS   (France)

Author keywords

Embedded memory; Formal verification; Timed automata; Timing analysis

Indexed keywords

AUTOMATA THEORY; ELECTRIC NETWORK ANALYSIS; EMBEDDED SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); TIMING CIRCUITS;

ABSTRACT FUNCTIONAL AND TIMING GRAPH; EMBEDDED MEMORY; TIMED AUTOMATA; TIMING ANALYSIS;

DATA STORAGE EQUIPMENT;

EID: 33747073314     PISSN: 11092734     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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