Verification of asynchronous circuits using timed automata

Electronic Notes in Theoretical Computer Science

Volumn 65, Issue 6, 2002, Pages 47-59

  Bozga, Marius ^a   Jianmin, Hou ^a   Maler, Oded ^a   Yovine, Sergio ^a  

^a VERIMAG   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTATIONAL METHODS; FINITE AUTOMATA; FUNCTIONS; GRAPHIC METHODS; LOGIC GATES;

ASYNCHRONOUS CIRCUITS; CIRCUIT VERIFICATION; SIGNAL TRANSITION GRAPHS (STG); TIMED AUTOMATA;

COMBINATORIAL CIRCUITS;

EID: 0346868287     PISSN: 15710661     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1571-0661(04)80468-7     Document Type: Conference Paper

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