Using a communication generator in SoC architecture exploration

2003 International Symposium on System-on-Chip, SoC 2003 - Proceedings

Volumn , Issue , 2003, Pages 105-108

  Kangas, Tero ^a   Riihimäki, Jouni ^a   Salminen, Erno ^a   Kuusilinna, Kimmo ^a   Hämäläinen, Timo D ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION MODELS; ARCHITECTURE EXPLORATION; ON-CHIP COMMUNICATION NETWORKS; PROCESS NETWORKS; SOC ARCHITECTURE; TASK PARTITIONING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 26444440167     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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