DATE panel chips of the future: Soft, crunchy or hard?

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 844-849

  Paulin, Pierre G ^a  

^a STMICROELECTRONICS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC STANDARD PRODUCTS (ASSP); ELECTRONIC PRODUCTS; NON-RECURRING EXPENSES (NRE); PROGRAMMABLE PROCESSORS; 90 NM TECHNOLOGY; CAD TOOL; DOMAIN SPECIFIC; ELECTRONIC PRODUCT; STANDARD CELL;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRONIC EQUIPMENT; ELECTRONICS ENGINEERING; ENCODING (SYMBOLS); FIELD PROGRAMMABLE GATE ARRAYS; PRODUCTIVITY; PROGRAM COMPILERS; PROGRAM PROCESSORS; SEMICONDUCTOR MATERIALS; EXHIBITIONS;

MICROPROCESSOR CHIPS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 3042561692     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268990     Document Type: Conference Paper

References (5)

1. th Design Automation Conference (DAC), Anaheim, June 2003.
2. H. Michel, A. Worm, M. Muench, N. Wehn, "Hardware/Software Tradeoffs for Advanced 3G Channel Coding", Proc. of Design Automation and Test in Europe (DATE), Paris, March 2002.
3. Tensilica Inc. http://www.tensilica.com
4. M. J. Thul, F. Gilbert, T. Vogt, G. Kreiselmaier, N. Wehn, "A Scalable System Architecture for High-Throughput Turbo-Decoders", Proc. 2002 Workshop on Signal Processing Systems (SiPS '02), pp. 152-158, San Diego, Oct. 2002.
5. F. Gilbert, M. Thul, N. Wehn, "Communication Centric Architectures for Turbo-Decoding on Embedded Multi-processors", Proc. of Design Automation and Test in Europe (DATE), pp. 356-361, Munich, March 2003.