New superjunction LDMOST with N-buffer layer

IEEE Transactions on Electron Devices

Volumn 53, Issue 8, 2006, Pages 1909-1913

  Park, Il Yong ^a   Salama, C Andre T ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

CMOS compatible process; Lateral; N buffer layer; Power MOSFET; Shallow pillar height; Substrate assisted depletion effects; Superjunction (SJ)

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; SEMICONDUCTOR JUNCTIONS; SUBSTRATES;

CMOS COMPATIBLE PROCESS; N-BUFFER LAYER; SHALLOW PILLAR HEIGHT; SUBSTRATE-ASSISTED DEPLETION EFFECTS; SUPERJUNCTION (SJ);

MOSFET DEVICES;

EID: 33746646020     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.877007     Document Type: Article

References (11)

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