Low power multiplication algorithm for switching activity reduction through operand decomposition

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 21-26

  Ito, Masayuki ^a   Chinnery, David ^b   Keutzer, Kurt ^b  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ENERGY UTILIZATION; LOGIC GATES;

COMPLEX CIRCUITS; POWER DISSIPATION;

LOGIC CIRCUITS;

EID: 0344119504     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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