On area-efficient low power array multipliers

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2001, Pages 1429-1432

  Wang, Yuke ^a   Jiang, Yingtao ^a   Sha, Edwin ^a  

^a The University of Texas at Dallas   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDER CIRCUIT; AREA EFFICIENT; ARRAY MULTIPLIERS; COMPUTATIONAL SYSTEM; CRITICAL OPERATIONS; FULL ADDERS; HSPICE SIMULATIONS; INTERNAL CAPACITANCE; LOW POWER; MODIFIED BOOTH MULTIPLIERS; MULTIPLICATION ALGORITHMS; PARALLEL MULTIPLIERS; POWER CONSUMPTION; POWER DISSIPATION;

CAPACITANCE; FREQUENCY MULTIPLYING CIRCUITS; MULTIPLEXING; MULTIPLEXING EQUIPMENT;

ADDERS;

EID: 0001736769     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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