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Volumn 2005, Issue , 2005, Pages 1739-1742

New designs of 14-transistor PPM adder

Author keywords

Low power adder; On line multiplier; PPM adder; Redundant binary system

Indexed keywords

ALGORITHMS; MICROPROCESSOR CHIPS; SUMMING CIRCUITS; TRANSISTORS;

EID: 33751350291     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2005.1557319     Document Type: Conference Paper
Times cited : (6)

References (6)
  • 4
    • 84937078021 scopus 로고
    • Signed digit number representation for fast parallel arithmetic
    • Sept.
    • A. Avizienis, "Signed digit number representation for fast parallel arithmetic," IRE Transactions on Electronic Computers, vol. EC-10, pp. 389-400, Sept. 1961.
    • (1961) IRE Transactions on Electronic Computers , vol.EC-10 , pp. 389-400
    • Avizienis, A.1
  • 5
    • 0001484299 scopus 로고
    • High-speed VLSI arithmetic processor architectures using hybrid number representation
    • April
    • H.R.Srinivas, et al., "High-speed VLSI arithmetic processor architectures using hybrid number representation," Journal of VLSI signal processing, vol. 4, pp.177-198, April 1992.
    • (1992) Journal of VLSI Signal Processing , vol.4 , pp. 177-198
    • Srinivas, H.R.1
  • 6
    • 0036476973 scopus 로고    scopus 로고
    • Performance Analysis of Low-Power 1-bit CMOS full Adder cells
    • Feb
    • Ahmed M. Shams et al., "Performance Analysis of Low-Power 1-bit CMOS full Adder cells," IEEE Trans. On VLSI systems, vol.10. No.1 Feb, 2002.
    • (2002) IEEE Trans. on VLSI Systems , vol.10 , Issue.1
    • Shams, A.M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.