Design for testability of an asynchronous adder

IEE Colloquium (Digest)

Volumn , Issue 40, 1996, Pages

  Petlin, O A ^a   Farnsworth, C ^b   Furber, S B ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

^b Bruntwood Hall ^*  (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DATA PROCESSING; DIGITAL ARITHMETIC; ENCODING (SYMBOLS); FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; MATHEMATICAL MODELS;

ASYNCHRONOUS ADDER; ASYNCHRONOUS CIRCUITS; DATA ENCODING; DESIGN FOR TESTABILITY; FAULT MODEL; SIGNALLING PROTOCOLS;

ADDERS;

EID: 0030385916     PISSN: 09633308     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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