Platform architecture design for MPEG-4 video coding

IEEE International Conference on Image Processing

Volumn 3, Issue , 2003, Pages 93-96

  Chao, Wei Min ^a   Chang, Yung Chi ^a   Hsu, Chih Wei ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SOFTWARE; COST EFFECTIVENESS; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE COMPRESSION; INTERPOLATION; MOTION ESTIMATION; OPTIMIZATION; REAL TIME SYSTEMS; TEXTURES;

PLATFORM ARCHITECTURE DESIGN; VIDEO ENCODERS;

IMAGE CODING;

EID: 0345565763     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A.Hatabu and et al., "QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General Purpose DSP," SIPS, vol. 23, pp. 27-49, 2002.
2. T.Kumura and et al., "VLSI DSP for Mobile Applications," IEEE Signal Processing Magazine, vol. 23, pp. 27-49, 2002.
3. M. Takahashi and et al., "An MPEG-4 Video LSI with an Error-Resilient Codec Core Based on a Fast Motion Estimation Algorithm," IEEE International Solid-State Circuits Conference, vol. 35, pp. 1713-1721, Feb 2002.
4. M. Takahashi and et al., "A 60-MHz 240-mW MPEG-4 Videophone LSI with 16-Mb Embedded DRAM," IEEE Journal of Solid-State Circuit, vol. 35, pp. 1713-1721, Nov 2000.
5. J.H. Park and et al., "MPEG-4 Video Codec on an ARM core and AMBA," MPEG-4 Proceedings of Workshop and Exhibition, vol. 35, pp. 95-98, June 2001.
6. C.W. Hsu, W.M. Chao, Y.C. Chang, and L.G. Chen, "Cost-Effective Scheduling Of Texture Coding For MPEG-4 Video," IEEE International Conference on Multimedia and Expo(ICME'02), Aug 2002.
7. T. Sikora, "The MPEG-4 Video Standard Verification Model," IEEE Trans. on Circuits and Systems for Video Technology, vol. 7, no. 1, pp. 19-31, Feb 1997.