Path-oriented transition fault test generation considering operating conditions

Proceedings of the 10th IEEE European Test Symposium, ETS 2005

Volumn 2005, Issue , 2005, Pages 54-59

  Seshadri, B ^a   Pomeranz, I ^a   Reddy, S M ^b   Kundu, S ^c  

^a PURDUE UNIVERSITY   (United States)

^b University of Iowa   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

JUNCTION TEMPERATURE; MULTIPLE OPERATING CONDITIONS; N-DETECTION;

ELECTRIC POTENTIAL; NETWORKS (CIRCUITS); POWER SUPPLY CIRCUITS;

ELECTRIC FAULT CURRENTS;

EID: 33744502392     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2005.31     Document Type: Conference Paper

References (14)

1. J.A.Waicukauski, E.Lindbloom, B.K.Rosen and V.S.Iyengar, "Transition fault simulation", IEEE Design and Test of computers, pp 32-38, Apr. 1987.
2. G.L.Smith, "Model for delay faults based upon paths", Proc. International Test Conference, pp 342-349, Sep. 1985.
3. W.Li., S.M.Reddy and S.K.Sahni,"On path selection in combinational logic circuits", IEEE Trans, on CAD of Integrated Circuits & Systems, vol. 8, pp. 56-63, Jan. 1989.
4. th Asian Test Symposium, pp.1-8, Nov. 2002.
5. K.D.Wagner and E.J.McCluskey, "Effect of supply voltage on circuit propagation delay and test applications", Proc. International Conference CAD, pp 42-44, 1985.
6. A.Gattiker, S.Nassif, R.Dinakar and C.Long, "Static Timing Analysis based circuit-limited yield estimation", Proc. IEEE ISCAS, vol. 5, pp 81-84. 2002.
7. th VLSI Test Symposium, pp 268-274, Apr. 1999.
8. R.D.S. Blanton, K.N.Dwarakanath and A.B.Shah, "Analyzing the effectiveness of multiple-detect test sets", Proc. International Test Conference, pp 876-885, Sep. 2003.
9. S.C.Ma, P.Franco and E.J.McCluskey, "An experimental chip to evaluate test techniques experimental results", Proc. of International Test Conference, pp 663-672, Oct. 1995
10. C.W. Tseng and E.J.McCluskey, "Multiple-output propagation transition fault test", Proc. of International Test Conference, pp 358-366, Oct. 2001
11. th VLSI Test Symposium, pp 173-180, Apr. 1999
12. th Great Lakes Symposium on VLSI, pp 282-287, Mar. 1996.
13. K.J. Nurmela and P. R. J. Ostergard, "Packing up to 50 equal circles in a square," Discrete & Computational Geometry, Vol. 18, pp. 111-120, 1997.
14. W.Qiu and D.M.H.Walker, "An efficient algorithm for finding the k-longest testable paths through each gate in a combinational circuit", Proceedings of International Test Conference, pp 592-601, Oct. 2003.