Diagnostic and detection fault collapsing for multiple output circuits

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 1014-1019

  Sandireddy, Raja K K R ^a   Agrawal, Vishwani D ^a  

^a AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC FAULT CURRENTS; FUNCTIONS; HIERARCHICAL SYSTEMS; LARGE SCALE SYSTEMS;

BOOLEAN CIRCUITS; CPU TIME; DIAGNOSTIC EQUIVALENCE;

COMBINATORIAL CIRCUITS;

EID: 33646948248     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.121     Document Type: Conference Paper

References (32)

1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. Piscataway, New Jersey: IEEE Press, 1990.
2. M. Abramovici, D. T. Miller, and R. K. Roy, "Dynamic Redundancy Identification in Automatic Test Generation," IEEE Trans. On CAD, vol. 11, no. 3, pp. 404-407, Mar. 1992.
3. V. D. Agrawal, A. V. S. S. Prasad, and M. V. Atre, "Fault Collapsing via Functional Dominance," in Proc. International Test Conf., 2003, pp. 274-280.
4. th VLSI Design & Test Workshops. Aug 2003.
5. S. B. Akers, C. Joseph, and B. Krishnamurthy, "On the Role of Independent Fault Sets in the Generation of Minimal Test Sets," in Proc. International Test Conf. 1987, pp. 1100-1107.
6. S. B. Akers and B. Krishnamurthy, "Test Counting: A Tool for VESI Testing,'' IEEE Design & Test of Computers, vol. 6, no. 5, pp. 58-77, Oct. 1989.
7. H. Al-Assad and R. Lee, "Simulation-Based Approximate Global Fault Collapsing," in Proc. International Conf. on VLSI, 2002, pp. 72-77.
8. th IEEE VLSI Test Symp., 2001, pp. 124-130.
9. th Design Automation Conf., June 1983, pp. 308-315.
10. M. E. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Boston, MA: Kluwer Academic Publishers, 2000.
11. W. T. Cheng and T. J. Chakraborty, "Gentest: An Automatic Test Generation System for Sequential Circuits," Computer, vol. 22, no. 4, pp. 43-49, April 1989.
12. F. W. Clegg, "Use of SPOOF's in the analysis of Faulty Logic Networks," IEEE Trans. Computers, vol. 22, no. 3, pp. 229-234, Mar. 1973.
13. th International Conf. VLSI Design. Jan. 2005, pp. 723-729.
14. T. Grüning, U. Mahlsdedt, and H. Koopmeiners, "DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits," in Proc. International Conf. CAD, Nov. 1991, pp. 194-197.
15. R. Hahn, R. Krieger, and B. Becker, "A Hierarchical Approach to Fault Collapsing," in Proc. European Design & Test Conf., 1994, pp. 171-176.
16. I. Hartanto, V. Boppana, and W. K. Fuchs, "Diagnostic Fault Equivalence Identification Using Redundancy Information & Structural Analysis," in Proc. International Test Conf. Oct. 1996, pp. 294-302.
17. M. A. Iyer and M. Abramovici, "FIRE: A Fault-Independent Combinational Redundancy Identification Algorithm," IEEE Trans. on VLSI Systems, vol. 4, no. 2, pp. 295-301, June 1996.
18. N. Jha and S. Gupta, Testing of Digital Systems. Cambridge University Press, 2003.
19. T. P. Kelsey, K. K. Saluja, and S. Y. Lee, "An efficient Algorithm for Sequential Circuit Test Generation," IEEE Trans. on Computers, vol. 42, no. 11, pp. 1361-1371, Nov. 1993.
20. A. Lioy, "Looking for Functional Fault Equivalence," in Proc. International Test Conf., Oct. 1991, pp. 858-863.
21. A. Lioy, "Advanced Fault Collapsing" IEEE Design & Test of Computers, vol. 9, no. 1, pp. 64-71, Mar. 1992.
22. A. Lioy, "On the Equivalence of Fanout-Point Faults," IEEE Trans. on Computers, vol. 42, no. 3, pp. 268-271, Mar. 1993.
23. E. J. McCluskey and F. W. Clegg, "Fault Equivalence in Combinational Logic Networks," IEEE Trans. on Computers, vol. C-20, no. 11, pp. 1286-1293, Nov. 1971.
24. th International Conf. VLSI Design, Jan. 2003, pp. 149-154.
25. M. Nadjarbashi, Z. Navabi, and M. R. Movahedin, "Line Oriented Structural Equivalence Fault Collapsing," in IEEE Workshop on Model and Test, 2000.
26. T. M. Niermann and J. H. Patel, "HITEC: A Test Generation Package for Sequential Circuits," in Proc. European Design Automation Conference, Feb. 1991, pp. 214-218.
27. th Annual Symposium on Switching Theory and Logic Design, Oct. 1964, pp. 121-132.
28. I. Pomeranz, E. N. Reddy, and S. M. Reddy, "COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits," IEEE Trans. CAD. vol. 12, no. 7, pp. 1040-1049, July 1993.
29. A. V. S. S. Prasad, V. D. Agrawal, and M. V. Atre, "A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets," in Proc. International Test Conf., Oct. 2002, pp. 391-397.
30. D. R. Schertz and G. Metze, "A New Representation for faults in Combinational Digital Circuits," IEEE Trans. On Computers, vol. C-21, no. 8, pp. 858-866, Aug. 1972.
31. K. To, "Fault Folding for Irredundant and Redundant Combinational Circuits," IEEE Trans. on Computers, vol. C-22, no. 11, pp. 1008-1015, Nov. 1973.
32. A. Veneris, R. Chang, M. S. Abadir, and M. Amiri, "Fault Equivalence and Diagnostic Test Generation Using ATPG," in Proc. IEEE International Symposium on Circuits and Systems, May 2004, pp. 221-224.