Using contrapositive law in an implication graph to identify logic redundancies

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 723-729

  Dave, Kunal K ^a   Agrawal, Vishwani D ^b   Bushnell, Michael L ^c  

^a ATI Research Inc   (United States)

^b AUBURN UNIVERSITY   (United States)

^c RUTGERS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

IMPLICATION GRAPHS; N-INPUTE GATES; TRANSITIVE CLOSURE METHOD;

GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; PROBLEM SOLVING;

DIGITAL CIRCUITS;

EID: 27944474338     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2005.166     Document Type: Conference Paper

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