Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 5, 2006, Pages 984-991

  Chou, Ju Ming ^a   Hsieh, Yu Tang ^a,b   Wu, Jieh Tsorng ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b Stanford University   (United States)

Author keywords

Averaging; Clocks; Delay locked loops (DLLs); Interpolation; Phase locked loops (PLLs)

Indexed keywords

DELAY CIRCUITS; DIGITAL CIRCUITS; ELECTRIC FREQUENCY MEASUREMENT; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTERPOLATION; PHASE LOCKED LOOPS; PHASE MEASUREMENT;

DELAY-LOCKED LOOPS; DIGITAL-TO-PHASE CONVERTER; PHASE AVERAGING; PHASE INTERPOLATION;

TIMING CIRCUITS;

EID: 33646513900     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.869905     Document Type: Article

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